The continuous scaling of transistor size makes it possible to integrate more and more signal processing functionalities into the same silicon with less area overhead. Employing extensive digital signal processing technologies, a digital radio processor (DRP) can process RF signals in the digital domain as much as possible to provide better performance with reduced cost. Based on an all digital PLL (ADPLL) architecture, a digital radio processor integrates all necessary blocks including RF, analog/mixed-signal and digital ones to provide a single-chip solution for GSM/GPRS/EDGE (GGE) and WCDMA applications.
The DRP receiver chain provides the signal processing for the received RF signals and includes both analog and digital blocks. Digital receiver (DRX) block provides RF signal processing in the digital domain. FIG. 1 illustrates the DRX architecture 100 including 9 blocks in the feed-forward path for GGE application. The DRX operates at two clock domains: channel-dependent ckvd64; and fixed ckres4X. These clock domain are bridged by the resampler (RES) 101. The Rate Change Filter (RCF1) 102 and Pre-Filter (PREF) 103 are located before RES 101. These blocks are driven by the ckvd64 clock derived from digital local oscillator (DLO). The other blocks operate at channel independent ckres4X clock domain and include a decimation finite impulse response (FIR) filter (RES) 104, IQMC computation engine (IQMC_CE) 105, residual offset cancellation infinite impulse response (IIR) filter (ROC_IIR) 106, zero-IF filter (ZIF) 107, channel select filter (CSF) 108 and droop cancellation filter (DCF) 109. The ROC_IIR can also be configured as high-pass (HPF) or low-pass (LPF) filters. The connection between these filters should be reconfigurable and it is currently implemented by a dedicated multiplexer block in DRPe. These blocks are referred as Fixed-rate Digital RX (FDRX) data path.
The current fixed-rate filtering blocks in the receiver chain (FDRX) of the digital radio processor (DRP) is implemented using fixed logic with very limited programmability. This makes it difficult to extend to support multi-standard wireless applications including GSM/GPRS/EDGE/WCDMA. Simply modifying the current GGE (GSM/GPRS/EDGE) FDRX by increasing the clock frequency cannot meet the WCDMA's sampling rate of 7.84 Msps without architectural change in those computationally-intensive blocks. Employing multiple dedicated data paths to cover these different standards would increase the area in proportion to the number of data paths. The flexibility problem needs to be resolved for the future multi-standard DRP products since providing both flexibility and performance is important for the low-cost 2G/2.5G/3G radio processors targeting the emerging market.
Currently the FDRX blocks shown in FIG. 1 are implemented by a fixed logic architecture. Each block operates at multiple clock domains to meet the data rate requirement of 1.083 Msps in GGE application. In this application specific integrated circuit (ASIC) each block is highly crafted to achieve the maximum efficiency in performance, area and power. The biggest pitfall of the fixed-logic architecture is the lack of configurability. Only limited intra-block connectivity is provided by the hardware multiplexes. This becomes worse when the DRP goes into 3G, where both 16-bit GGE and 8-bit/16 bit WCDMA modes are supported. Although WCDMA has less data width compared with GGE, its data path have different configurations which brings more complexity to the fixed-logic architecture. Supporting multiple wireless protocols on the same platform is becoming a natural trend with an increasing number of wireless applications. This requires maximum reconfigurability of FDRX to meet the data rate requirement.
Processor-based architecture has good flexibility and is controlled by instructions which share the common instruction fetch and decode logic. The execution of each instruction takes place in a heterogeneous functional unit. Most RISC processors are based on a load-store architecture, where memory access can only be implemented by a load (LD) instruction or a store (ST) instruction. This architecture simplifies the memory interface and the instruction set to achieve high operating frequency and throughput.
The trade-off in the general purpose processors is flexibility at the sacrifice of performance. In an experiment the GGE FDRX data path including the seven blocks illustrates in FIG. 1 was ported onto a 32-bit 8-issue high-performance general purpose DSP, the Texas Instruments TMS320C6201. The simulated sustaining data rate was only 90.49 Ksps, which is 11.96 times lower than the GGE requirement of 1.083 Msps under a 200 MHz clock frequency without any hardware customizations. Some customization of the processor's data path with application specific instructions is required to meet the performance requirement. This reduces the cycle count for computations in the FDRX critical path needed to meet the performance requirement. The customization of instructions doesn't reduce the processor's flexibility, but it provides a highly reconfigurable FDRX platform for the multi-mode 3G applications.